1. Field
The disclosed embodiments relates to the graphics processing, and more particularly to a graphics processing system with power-gating control function and a power-gating control method thereof, for dynamically predicting the required number of active shaders according to frame rate variations.
2. Description of the Related Art
Generally, graphics application programs involve complex and highly detailed graphics renderings, such as three-dimensional (3D) graphics. To meet current graphic program demands, graphics processing units (GPUs) have become an integral component of personal computers or portable devices to handle substantial amounts of computations for displaying various objects, thereby resulting in high power consumption or dissipation. Further, because power consumption is a major concern for battery-powered portable devices, such as mobile phones, it is necessary to reduce total power consumption induced by graphics processing units of mobile phones.
Power dissipation of electronic components typically comprises: dynamic power dissipation induced by voltage sources and operating frequencies; and static power dissipation caused by current leakage. Given the current state of semiconductor processing technologies, power dissipation from current leakage is a problem. For example, current leakage has exceeded 40% or more of the total power dissipation for semiconductor products fabricated using 65 nm process technologies.
Typically, clock-gating control techniques or dynamic voltage and frequency (DVFS) techniques are used to save power. Both are effective in decreasing dynamic power dissipation, but leakage power dissipation still remains, or may only be partially reduced. According to other conventional methods, such as power-gating control techniques, power-gating control elements are arranged over an entire graphics processing unit and the power supplied to the entire graphics processing unit is correspondingly controlled via the power-gating control elements. However, such a method lacks design flexibility. Additionally, power-gating control elements may be arranged inside of each component. When one component is idle, the power supplied thereto is turned off via a corresponding power-gating control element, so as to simultaneously reduce dynamic and static power loss. However, such a power-gating control mechanism requires an extra control circuit for turning on/off the power supplied to each component, which must consume power. In addition, the execution of the power-gating control function introduces a significant time overhead for resuming the power supplied to each component, thereby forming the power-gating control mechanism inefficient and time-consuming.
Therefore, it is desired to provide a graphics processing unit with improved power-gating control techniques that facilitates power saving based on the demands for different graphics application programs.